Efficient Parallel Fir Filter Implementations Using Frequency Spectrum Characteristics

Parallel (or block) FIR digital lters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel lter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an eecient parallel FIR lter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First the lter spectrum characteristics are exploited to select the best fast lter structures. Second, a novel block lter quantization algorithm is introduced. Using lter benchmarks, it is shown that the use of the appropriate fast FIR lter structures and the proposed quantiza-tion scheme can result in reduction in the number of binary adders ranging from 4% to 24% and an average reduction of about 10%. Furthermore, the power consumption of these lters is reduced by 14.8% on average and ranges from 10% to 20%.